1. Field of the Invention
Embodiments of the present invention generally relate to methods and processes for forming conformal silicon nitride films, including doped silicon nitride films, at low temperatures.
2. Description of the Related Art
The electronic device industry and the semiconductor industry continue to strive for larger production yields while increasing the uniformity of layers deposited on substrates having increasingly larger surface areas. These same factors in combination with new materials also provide higher integration of circuits per unit area on the substrate. As circuit integration increases, the need for greater uniformity and process control regarding layer characteristics rises.
For example, ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and which cooperate to perform various functions within an electronic device. Such transistors may include complementary metal-oxide-semiconductor (CMOS) field effect transistors. A CMOS transistor includes a gate structure that is disposed between a source region and a drain region defined in the semiconductor substrate. The gate structure (stack) generally comprises a gate electrode formed on a gate dielectric material.
Transistors may also be formed as 3 dimensional or 3D circuits as compared to traditional planar circuits. 3D transistors may employ gates that form conducting channels on three sides of a vertical “fin” structure, allowing chips to operate at lower voltage with lower leakage. Examples of three dimensional transistors having such gate structures include a FinFET (a nonplanar, double-gate transistor built on a silicon-on-insulator technology substrate, based on the earlier DELTA (single-gate) transistor design) or a Trigate transistor structure.
Conformal coverage with low pattern loading effect of dielectric films on high aspect ratio structures and/or 3D structures are of critical requirement as device node shrinks down to below 45 nm, such as to the 22 nm level, and as the manufacture of 3D transistors increases. Silicon nitride films, including doped silicon nitride, may be used throughout integrated circuit formation, such as gate spacers, liner layers, sacrificial layers, barrier layers, etc. Silicon nitride films, formed using thermal processes offers good conformality. The drawbacks, however, include a high temperature requirement (typically greater than 400° C.) and few capabilities to engineer film compositions and properties for different applications. Alternatively, conventional silane-based plasma enhanced chemical vapor deposition (PE-CVD) silicon nitride films have poorer step coverage due to directionality of radicals' fluxes. Additionally, tuning conformal layers to have desired film properties has also been difficult, particularly as the feature size decreases and the use of non-planar structures increases.
Therefore, there is a need for a low temperature, tunable process to form conformal silicon nitride films on substrates, especially as pattern density and structural aspect ratios increase and device structure sizes decrease.